The ever-increasing capacity of digital networking equipment poses increased demand on the interface speeds of today's complementary metal oxide semiconductor (CMOS) chips. At the same time, this increase has resulted in the need for CMOS technologies with smaller device geometries and thinner oxides that are more sensitive to damage due to Electrostatic Discharge (ESD).
The first line of defense against ESD is a pair of diodes, connected between pad and supply buses, that absorb the discharge current and limit the voltage between the bond pads or bumps (pins, if packaged) connecting the chip to the outside world.
FIG. 1 illustrates a typical scenario for a circuit with ESD diode protection. During an ESD event, in this example between the input/output pad and VSS, the discharge current passes either through the upper diode DP and a power clamp, to return to its source through the VSS pad (in case of a positive current) or enters the VSS pad, passes through the lower diode DN and exits through the I/O pad. In either case the sensitive internal circuitry is protected by the voltage-limiting properties of the ESD protection diodes that provide a discharge path around the circuitry.
In normal use the ESD diodes are reverse-biased and do not present a significant DC current path that might affect the normal operation of the circuit. They do possess capacitance, however, which poses an AC path to ground and may load and distort the received (or transmitted) signal at high frequencies. This capacitance is largely determined by the physical size (junction area) of the ESD diodes, which in turn is given by the amount of ESD current the diodes need to be able to absorb. Process technology has little influence: contrary to MOS devices, the intrinsic properties of junction diodes do not scale with process node. If anything, process nodes with smaller device geometries typically have thinner routing metals and smaller intra-level vias, making it even harder to provide a low-resistance and low-capacitance discharge path around the CMOS circuitry.
Although the processing speed of CMOS technology keeps increasing each time device feature sizes shrink, the junction area of the primary ESD protection diodes remains the same for a given level of protection. The parasitic capacitance associated with the diode junction limits the I/O bandwidth of receivers and transmitters of high speed integrated circuits (ICs). This limitation is manifest both in terms of return loss and insertion loss.
One method to mitigate the effect of diode capacitance is by using inductors that incorporate the capacitance into a low-pass structure, effectively “tuning out” or broad-banding the capacitance.
Assuming that the diodes are lumped, as opposed to distributed, there are three known methods (and possible combinations) of inductive tuning or broad-banding, as shown in FIGS. 2A, 2B and 2C. In these figures, on-chip termination and ESD protection are shown for a receiver circuit, and R denotes the termination resistor, which in an example implementation has a value of 50 0.
FIGS. 2A, 2B and 2C illustrate inductive broad-banding of ESD diode capacitance using shunt peaking, series peaking and T-coil peaking, respectively. Shunt peaking as shown in FIG. 2A provides a reasonable bandwidth extension (1.7×) of the received signal, as compared to the non-peaked case, but return loss is poor. Series peaking as shown in FIG. 2B can provide similar bandwidth extension with much improved return loss if the overall input capacitance CESD+CIN can be split by the peaking inductor. Superior bandwidth extension and return loss are achieved with the T-coil input match as shown in FIG. 2C. However, the protection diodes in FIG. 2C are not directly connected to the pad, and significant inductance is present between the pad and the ESD diodes.
The majority of ESD failures are caused by a discharge mechanism that is best-described by the Charged-Device Model (CDM) and its variants, in which devices are exposed to a charge at a standardized voltage level, then tested for survival. Discharge transients dl/dt in the CDM model are orders of magnitude higher than other models. Inductance in the discharge path between pad and diodes may cause high voltage peaks at the pad, leading to possible dielectric breakdown.
For all three methods of inductive peaking shown in FIGS. 2A, 2B, and 2C, the cut-off frequency is limited by the LC product of inductance and capacitance.
A distributed approach, breaking the diodes up in multiple, smaller, LC sections of an artificial transmission line allows the cut-off frequency to be pushed out much further in frequency than is possible with a single lumped diode. FIG. 3 illustrates a known distributed ESD protection approach. Very good return loss and insertion loss can be achieved in this manner. However, each diode will see a different voltage and current profile, especially during a sub-nanosecond CDM event, when the inductive properties of the discharge path weigh in along with the resistive ones. As a result, ESD protection is not as effective as when the diodes are lumped together.
It is desirable to provide an improved ESD protection circuit that addresses at least one of the shortcomings of known approaches.